1. Field of the Invention
The present invention generally relates to computer systems and, more particularly, to a method of simulating errors in the retrieval of information from a computer memory for testing an error detection or correction device.
2. Description of the Related Art
The basic structure of a conventional computer system 10 is shown in FIG. 1. The heart of computer system 10 is a central processing unit (CPU) or processor 12 which is connected to several peripheral devices, including input/output (I/O) devices 14 (such as a display monitor and keyboard) for the user interface, a permanent memory device 16 (such as a hard disk or floppy diskette) for storing the computer's operating system and user programs, and a temporary memory device 18 (such as dynamic random-access memory or DRAM) that is used by processor 12 to carry out program instructions. Processor 12 communicates with the peripheral devices by various means, including a bus 20 or a direct channel 22. Computer system 10 may have many additional components which are not shown, such as serial and parallel ports for connection to, e.g., modems or printers. There are other components that might be used in conjunction with those shown in the block diagram of FIG. 1; for example, a display adapter connected to processor 12 might be used to control a video-display monitor. Computer system 10 also includes firmware 24 whose primary purpose is to seek out and load an operating system from one of the peripherals (usually permanent memory device 16) whenever the computer is first turned on.
Parity checks and error-correction codes (ECCs) are commonly used to ensure that data is properly transferred between system components. For example, a magnetic disk (permanent memory device) typically records not only information that comprises data to be retrieved for processing, but also records an error correction code for each file, which allows the processor, or a controller, to determine whether the data retrieved is valid. ECCs are also used with temporary memory devices, e.g., DRAM, and the ECC for files stored in DRAM can be analyzed by a memory controller which provides an interface between the processor and the DRAM array. If a memory cell fails during reading of a particular memory word (due to, e.g. stray radiation, electrostatic discharge, or a defective cell), then the failure can at least be detected so that further action can be taken, e.g., re-trying the read operation to see if the failure occurs again, as taught in U.S. Pat. No. 4,360,915. ECCs can further be used to reconstruct the proper data stream. See, e.g., U.S. Pat. No. 4,561,095 which discloses a high-speed error correcting a random-access memory system which uses a plurality of parity bits stored in memory along with the associated data bits.
Some error correction codes can only be used to detect single-bit errors, i.e., if two or more bits in a particular memory word are invalid, then the ECC might not be able to determine what the proper data stream should actually be. Other ECCs are more sophisticated and allow detection or correction of double errors, and some ECCs further allow the memory word to be broken up into clusters of bits, or "symbols," which can then be analyzed for errors in more detail.
Parity and error-correcting code DRAM controllers need special hardware to generate simulated errors, including both single and multi-bit errors. This hardware generates data patterns which, in turn, are used to generate fault data in real-time. This hardware is relatively expensive and, further, leaves the system response to actual memory errors untested in the development phase and manufacturing phase. It would, therefore, be advantageous to devise an inexpensive hardware technique to generate single- and multiple-bit memory errors which can be used with actual system memory. It would be further advantageous if the hardware could also be used with a memory controller which has no internal means of testing parity or ECC circuitry.